The present invention relates to microelectronic devices and, and more specifically, to testing structures within laminates for such devices.
Once formation of semiconductor devices and interconnects on a semiconductor wafer is completed, the semiconductor wafer is diced into semiconductor chips, or “dies.” Functional semiconductor chips are then packaged to facilitate mounting to a larger device.
The packaging generally provides mechanical protection and electrical connections to an external element. One typical packaging technology is Controlled Collapse Chip Connection (C4) packaging, which employs C4 balls each of which contacts a C4 pad on the semiconductor chip and another C4 pad on a packaging substrate.